Methods and means of parallel order reduction of super-large RLC circuits models

Project scientific manager is Professor A.I. Petrenko.

Aim of scientific-research work is development of new approaches and methods of order reduction of mathematical RLC circuits, which describe connections in VLSI/ These approaches are based on macromodeling ideas with the use of Y-Δ transformation, which allows (with minimal accuracy losses from the point of view of signal delay) to reduce the sizes of RLC circuit model at least on 85%. According to the tasks size (up to several millions components), respective calculation algorithms are realized in the form of parallel procedures which contain specially developed effective and quick algo­rithms of storing, search and conversion of information in the super-large data blocks. Programming tools designed are integrated into the ALLTED (Kyiv, NTUU «KPI»), the native circuit simulator, and are functioning under parallel PVM calculations in operational environments like Windows or Unix.


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